The present invention relates to branch prediction logic (BPL), and more specifically, to silent mode and resource reassignment in BPL.
In a computing system such as a microprocessor, branch instructions are used to implement control flow constructs such as conditionals or loops. When the branch that will be taken can be predicted, it facilitates a prefetch of parameters and a speculative execution of instructions subsequent to the branch instructions. When the actual branch resolution (branch direction and target) is equal to the predicted branch direction and target, this prefetch and speculative processing can increase speed and efficiency.